It is a known fact that read-only circuit structures or ROMs (Read-Only Memories) are basically comprised of regular cell arrays.
The memory is programmed, in general, by making some predetermined cells nonconductive, thereby logic signals are output which are tied to the value of the input signals in a sought relationship.
Each cell basically comprises a transistor operating on a gate voltage Vg of 5 volts. That is, all the gates of the cells in the array are connected to a common 5-volt power source.
Between a programmed cell and a nonprogrammed one, there should be a current difference of some hundreds microamperes to permit of discrimination therebetween during the read-out stage.
In order to obtain a large difference between such currents, the prior art has commonly proposed of raising the conduction threshold of the corresponding transistors to the cells to be programmed. This can be achieved by increasing the surface concentration of dopant in the transistor channel region, e.g., by the additional implantation of type "p" impurities with boron ions for an n-channel transistor.
However, the high surface concentration of the channel region and high doping of the adjacent drain region of the transistor cause the drain depletion zone to become small, which results in the drain capacitance becoming relatively high while the breakdown voltage is comparatively low.
In view of that the drain electrodes form the so-called bit line of a ROM, this bit line will exhibit a long charge time reflecting in a long access time to the memory.